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1.1 2 3 data sheet revision 1.1, 04-april-06 www.austriamicrosystems.com page 1 of 40 1 features ? 16 bits resolution ? differential inputs ? single + 5v supply ? low power 15 mw ? soic16 package ? self- and system-calibration with auto-calibration on power up ? 16 khz maximum sampling frequency ? internal temperature measurement ? internal factory trimmed precision reference ? programmable current sources ? digital comparator ? active wake-up ? pga gains 1, 6, 24, 50, 100 ? zero offset ? zero offset tc ? extremely low noise ? internal oscillator with comparator for active wake up ? 3-wire serial interface, p compatible ? temperature range ? 40 to + 125 c ? individual 24-bit serial number 2 applications ? battery management for automotive systems ? power management ? mv/v-meter ? high-precision voltage and current measurement 3 general description the AS8501 is a complete, low power data acquisition system for very small signals (i.e. voltages from shunt resistors, thermocouples) that operates on a single 5 v power supply. the chip powers up with a set of default conditions at which time it can be operated as a read-only-converter. reprogramming is at any time possible by just writing into two internal registers via the serial interface. the AS8501 has four ground refering inputs which can be switched separately to the internal pga. two input channels can also be operated as a fully differential ground free input. the system can measure bo th positive and negative input signals. the pga amplification ranges from 6 to 100 which enables the system to measure signals from 7mv to 120 mv full scale range with high accuracy, linearity and speed . the chip contains a high precision bandgap reference and an active offset compensation that makes the system offset free (better than 0,5 v) and the offset-tc value negligible. the built- in programmable digital filter allows an effective noise suppression if the high speed is not necessary in the application. the input noise density is only 35 nv / hz and due to the high internal chopping frequency the system is free of 1/f-noise down to dc.the 0-10 hz noise is typical below 1 v i.e. as good or better than any other available chopper amplifier. for high speed synchronous measurements the chip can run in an automatic switching mode between two input channels with pre- programmed parameter sets. the circuit has been optimised for the application in battery management systems in automotive systems. as a front end data acquisition system it allows an high quality measurement of current, voltage and temperature of the battery. with a high quality 100 ? resistor the system can handle the starter current of up to 1500 a, a continuous current of 300 a as well as the very low idle current of a few ma in the standby mode. for external temperature measurement the chip can use a wide variety of different temperature sensors such as rtd, ptc, ntc, thermocouples or even diodes or transistors. a built-in programmable current source can be switched to any input and activate these sensors without the need of other external components. the measurement of the chip temperature with the integrated internal temperature sensor allows in addition the temperature compensation of sensitive parameters which increases the total accuracy considerably. sensor specific data can be stored in the internal zener-zap memory and are used to calibrate each measurement in the internal data processing unit before transmission to the external c via the serial sdi interface. the flexibility of the system is further increased by a digital comparator that can be assigned to any measured property (current, voltage, temperature) and an active wake-up in the sleep-mode. all analog input-terminals can be checked for wire break via the sdi- interface. internal temperature input mux chopper protection current sources etr ets rshh rshl vbat 16 bit - converter buf serial interface / control registers dsp controller filter int. clock timer calibration data comparator 1.26 v reference sclk sdat intn ref agnd vdda vssa vddd vssd clk ezprg pga and level shift AS8501 preliminary data sheet high precision voltage and current measurement sensor interface fi g ure 1: functional block dia g ram
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 2 of 40 contents 1 features....................................................................................................................... ..................................................................1 2 applications ................................................................................................................... ..............................................................1 3 general description............................................................................................................ .....................................................1 4 pin function descriptio n for soic 16 package................................................................................... ............................3 5 absolute maximum ratings....................................................................................................... ..............................................4 6 electrical c haracteristics ..................................................................................................... .............................................5 7 functional description ......................................................................................................... ..................................................9 7.1 p ower on r eset ............................................................................................................................... ............................................9 7.2 a nalog part , general description ............................................................................................................................... ..............9 7.2.1 reference voltage .............................................................................................................. ...............................................10 7.2.2 current sources................................................................................................................ .................................................11 7.2.3 internal temperature sensor .................................................................................................... ..........................................12 7.3 d igital part ............................................................................................................................... ..................................................12 7.3.1 sampling rate .................................................................................................................. ..................................................12 7.3.2 calibration .................................................................................................................... .....................................................13 7.4 m odes of operation ............................................................................................................................... ....................................13 7.5 r egister description ............................................................................................................................... ..................................15 7.5.1 opm operation mode register ( 4 bits ) ......................................................................................... ....................................16 7.5.2 crg general configuration register ( 28 bits )................................................................................. ..................................16 7.5.3 cra measurement channel a configuration register ( 17 bits ) ................................................................. .....................17 7.5.4 crb measurement channel b configuration register ( 17 bits ) .................................................................. .....................19 7.5.5 zzr zener-zap register (188 bits )............................................................................................ .......................................20 7.5.6 car calibration register ( 110 bits ) ......................................................................................... ........................................22 7.5.7 trr trimming register ( 20 bits ) .............................................................................................. .........................................22 7.5.8 thr alarm (wake-up) threshol d register ( 17 bits ) ............................................................................ .............................25 7.5.9 msr measurement result register ( 18 bits )................................................................................... .................................25 8 digital interface description.................................................................................................. ...........................................25 8.1 clk............................................................................................................................ ..................................................................25 8.2 intn ........................................................................................................................... .................................................................25 8.3 sdi bus operation ............................................................................................................................... .......................................26 8.4 d ata transfers ............................................................................................................................... ...........................................27 8.5 sdi bus timing ............................................................................................................................... ..............................................28 8.6 sdi access to otp memory ............................................................................................................................... .........................29 8.6.1 zzr register bit mapping....................................................................................................... ............................................29 8.6.2 stored zzr-register mapping.................................................................................................... ........................................33 9 general application hints ...................................................................................................... .............................................34 9.1 g round connection , analog common ............................................................................................................................... ........34 9.2 t hermal emf ............................................................................................................................ ..................................................34 9.3 n oise considerations ............................................................................................................................... ..................................35 9.4 s hielding , guarding ............................................................................................................................... .....................................35 10 typical performance characteristics ............................................................................................ ..............................36 11 package dimensions ............................................................................................................. ...................................................38 12 revision history............................................................................................................... .........................................................38 13 ordering information ........................................................................................................... .................................................38 14 contact........................................................................................................................ .................................................................39 14.1 h eadquarters ............................................................................................................................... ........................................39 14.2 s ales o ffices ............................................................................................................................... .........................................39
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 3 of 40 4 pin function description for soic 16 package pin name description comment 1 rshl anlalog input from shunt resistor low side analog common for vbat, ets and etr; return for internal current source 2 rshh anlalog input from shunt resistor high side 3 ets analog input with reference to rshl analog input for diff erential input ets-vbat analog output for current-source 4 vbat analog input with reference to rshl analog input for diff erential input ets-vbat analog output for current-source 5 vss 0v-power supply for analog part 6 ezprg digital power input for programming zener fuses. this input must be ope n or connected to vddd. it is not intended, that otp content is modified by the user. 7 vssd 0v-power supply and ground reference poi nt for digital part 8 clk digital input for external clock, master clock input external clock typical 8.192 mhz; during mwu-mode external connection must be high impedanc e or connected to vddd to reduce current consumption 9 sclk serial port clock input for sdi-port the user must provide a serial clock on this input 10 sdat serial data in- and output 11 intn digital i/o for interrupt from comparator signal wake-up to external c conversion ready flag for external interupt and synchronisation in normal mode 12 vddd + 5v digital power supply 13 vdda + 5v analog power supply 14 ref reference input/output must be connected to vss with a 30 nf capacitor 15 agnd analog ground, ground reference for adc this pin must be connected with a 50-100nf-capacitor to vss; no direct connection to vssd/vss allowed 16 etr analog input with reference to rshl analog output for current-source table 1: pin description fi g ure 2: schematic packa g e outline soic 16
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 4 of 40 5 absolute maximum ratings stress beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions beyond those indicated under ?operating conditions? is not implied. ex posure to absolute maximum rating conditions for extended periods may affect device reliability. all voltages are defined with respect to vss and vssd. positive currents flow into the ic. absolute maximum ratings (t a = -40c to 125c unless otherwise specified) nr. parameter symbol min typ max unit note 0 supply voltage analogue vdda and digital vddd vdd -0.3 7.0 v polarity inversion externally protected 1 input pin voltage v in -0.3 vdd +0.3 v 2 input current (latch-up immunity) i scr -100 100 ma jedec 17 3 electrostatic discharge esd -2 2 kv 1) 4 ambient temperature t a -40 125 o c (tj = 150c) 5 storage temperature t strg -55 150 o c 6 soldering conditions t lead 260 c 2) 7 humidity, non-condensing 5 85 % 8 thermal resistance r thja 75 k/w 9 power dissipation p tot 350 mw notes: 1) mil 883 e method 3015, hbm: r =1.5 k , c =100pf. 2) jedec std ? 020c, lead free
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 5 of 40 6 electrical characteristics vdda=5v +/-0.1 v, fclk=8.192 mhz, chopping ratio mm=4 (see 7.5.3), oversampling frequency=2.048 mhz, oversampling ratio=128 temperature range : -40 to 125c if not otherwise noted symbol parameter conditions min typ max units input characteristics g1 for gain 1 the input signal is connected directly to th input of the converter, this is not possible for the rshh-rshl input gain gains of pga 6, 24, 50, 100 1) ac_g6 accuracy at gain 6 0 to 85 c 1.0 % @-120mv 2) -40 to 125c 1.5 % @-120mv 3),4) ac_g24 accuracy at gain 24 0 to 85 c 0.5 0.08 % @+-20mv 2) -40 to 125c 1.5 0.3 % @+-20mv 3) 4) ac_g50 accuracy at gain 50 0 to 85 c 1.0 % @+-10mv 4) ac_g100 accuracy at gain 100 0 to 85 c 1.0 % @+-5mv 4) vin input voltage ranges g1 -350 -300 to + 800 900 mv 5) 6) (with reference to rshl) g6 -200 +/- 120 160 mv 5) 7) g24 -40 +/- 30 40 mv 5) 7) g50 -20 +/- 15 20 mv 5) 8) g100 -10 +/- 7.5 10 mv 5) 8) notes: 1) the absolute gain values are subjected to a manufacturing spread of +/-30% max in the full temperature range. all gain values can be digitally calibrated together with the external circuitry with a resolution better than 0.065% 2) current measurement paths for g6 and g24 are trimmed for minimum temperature coefficient. the trimm algorithm is based on a 2 temperature measurement at 23c and 60c. accuracy is mainly determined by bandgap characteristic and gain variation over temperature. a tc shift of typically -15 ppm/k will occure during solder process which is compensated by a systematic offset during trimming . 3) due to a nonlinear behaviour of the gain and reference voltage over temperature the accuracy is lower for the extended tempera ture range. 4) the minimum limits for g50, g100 are derived from device characterization and not tested. towards 125c the tc values are high er. therefore it is recommended to use these gain settings only for applications in the temperature range 0 to 85c. 5) if not otherwise specified the ranges are calibrated to the typical values. the maximum and minimum value represent the maxim um usable span accepting linearity deviation up to 1000 digits. min, max limits are tested at room temperature only! 6) this gain range is not using the internal pga, the input is directely connected to the ad-converter. therefore the input resis tance is lower then for other gain ranges. it has been designed mainly for positive input voltages up to 0.8 v i.e. for measurements of temperature with transistors and d iodes. the limitation for negative input voltages is due to the onset of conduction of the input protection diodes. 7) the asic is optimised for g6 and g24 concerning linearity, s peed and tc, therefore these ranges are recommended whenever possi ble. 8) because of higher tc value at elevated temperature g50 and g100 are recommended for applications in the temperature range 0 to 85c
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 6 of 40 electrical characteristics (continued) vdda=5v +/-0.1 v, fclk=8.192 mhz, chopping ratio mm=4 (see 7.5.3), oversampling frequency=2.048 mhz, oversampling ratio=128 temperature range : -40 to 125c if not otherwise noted symbol parameter conditions min typ max units cal_err calibration error for 30 000 digits output at full range g1, 720 mv g6, 120 mv g24, 30 mv g50, 15 mv g100, 7.5 mv 0.1 0.2 % 1) lin_err nonlinearity gain 6 @ room temp 0.1 0.3 % or 30 digits 2) gain 24 @ room temp 0.03 0.05 % or 10 digits 2) gain 50 @ room temp 0.05 0.07 % or 15 digits 2) gain 100 @ room temp 0.05 0.1 % or 20 digits 2) lin_errtc tc of linearity error all gains 1 5 ppm/k 3) vos offset voltage: rshh_rshl -40 to 125c -0.5 0.2 0.5 v 4) offset voltage: ets, etr, vbat -40 to 85c -2 0.5 1 v 4) 85 to 125c -4 1 2 v 4) dvos/dt offset voltage drift: rshh- rshl -40 to 85 c 0.002 v/k ib input bias/leakage current, all channels room temperature -1 0.2 1 na 5) vndin voltage noise density (g=24) f=0 to 1 khz 35 50 nv//hz 6) indin current noise density (g=24) f=10 hz 5 20 100 fa//hz 6) en p_p voltage noise, peak (g=24) 0 to 100 hz 2 3 5 v 6) 0 to 10 hz 0.5 1 1.5 v 6) en_rms voltage noise, rms (g=24) 1000 hz 1.5 2 v snr signal to noise (g=24, g4.8) room temperature 90 100 dbmin sdr signal to distortion (g24, g4.8) room temperature 80 100 dbmin cci chanel to chanel insulation room temperature -70 -90 dbmax psrr power supply rejection ratio 4.9 to 5.1 v -50 -60 dbmax notes: 1) at room temperature / corresponding calibration factors are stored within the zzr-register 2 ) whatever is lower. maximum limits for gains 50 and 100 are derived from device characterization and are not tested. 3) this value measured in raw mode at room temperature and at 60c. maximum limits over temperature range are derived from device characterization. 4) tc variations are included in the above given maximum limit of linearity error. max value is derived from device characterizat ion and not tested 5) leakage current is specified for all gain settings (except g1) for positive input voltages below 200 mv. test is done at diff erent input voltages with subsequent extrapolation for 200mv. in the temperature range 85-125c it may be as high as 5 na at the upper limit. in normal o peration a temperature independent digital offset of -0.7 digits is present due to internal rounding. 6) this parameter is not measured directly. it is measured indirectly via gain measurement of the whole path at room temperature
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 7 of 40 electrical characteristics (continued) vdda=5v +/-0.1 v, fclk=8.192 mhz, chopping ratio mm=4 (see 7.5.3), oversampling frequency=2.048 mhz, oversampling ratio=128 temperature range : -40 to 125c if not otherwise noted symbol parameter conditions min typ max units data conversion res resolution all channels 16 bits 1) 2) vref reference voltage room temperature 1.13 1.21 1.30 v 3) vref_tc temperature coefficient of vref -50 50 ppm/k 4) vref_ri internal resistance of vref rload > 50 kohm 200 ohm fovs clock frequency 4.096 mhz r1 oversamplig ratio 64 128 mm conversions during chopper cycle 4 8 bw bandwidth 7.8 1000 16000 hz av internal averaging 1 4 1024 cycles fclk external clock frequency 0.05 8.192 10 mhz 5) clk_extdiv clock division factor 2 4 dr_clk duty ratio of external clock 50 % int_fclk internal clock frequency 180 250 330 khz analog inputs rshh, vbat, ets, ets rin input resistance ue < 150 mv 50 100 mohm cin input capacitance at gain 24 8 15 30 pf internal temperature sensor t_out20 output at 23c g 6, typical 22500 23 000 23500 digits 6) t_sl slope -20 to 100c 73 75 77 digits/degc 7) terr85 error of temperature measurement 0 to 85c 0.5 2 degc 7) terr125 -40 to 125c 1 3 degc 7) current source output to rshh, rshl icurr_rshh 1.5 2 3 a notes: 1) with external averaging the resolution can be increased up to 21 bits with an effective sampling rate below 10 hz 2 ) the system works in overflow condition without degradation of accuracy up to 1.4 * range width. this means that the overflow bit can work as bit no.17 in this range. 3) the absolute value will be trimmed digitally to (1.28*/-0.01) v at 23c, if not otherwise specified 4) the tc-value will be trimmed digitally to end up with a typical tc-value of the output ( total measurement path) at g24 bette r than 20 ppm/k the tc- value of the reference voltage after trimming may be typically as high as 50 ppm/k due to manufacturing spread. min,max limits are not tested but derived from device characterization 5) in the temperature range 0 - 85c the clock frequency can be increased to 12 mhz 6) value trimmed to +/- 30 digits during final test and stored into zzr 7) the slope of the sensor is measured on sample basis per lot and not tested per device. the specified limits are derived from de vice characterization.
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 8 of 40 electrical characteristics (continued) vdda=5v +/-0.1 v, fclk=8.192 mhz, chopping ratio mm=4 (see 7.5.3), oversampling frequency=2.048 mhz, oversampling ratio=128 temperature range : -40 to 125c if not otherwise noted symbol parameter conditions min typ max units programmable current source output to vbat, ets, or etr icurr_on current level 0 248 a i_steps current steps 6 8 10 a dcurr accuracy, room temperature 248 a 0.2 0.5 % tc_cs temperature coefficient 830 900 1000 ppm/k 1 ) icurr_off current when off room temperature 0.001 0.01 a icurr_ri internal resistance of current source ua < 2 v 10 mohm digital cmos inputs with pull up and schmidt-trigger input pins clk and sclk vih high level input voltage vddd=5v 3.5 v vil low level input voltage vddd=5v 1.5 v iih current level vddd=5v, vih=5v -1 1 a iil current level vddd=5v, vil=0 30 120 a digital cmos outputs output pins sdat and intn voh high level output voltage vddd=5v, -633ua 4.5 v vol low level output voltage v ddd=5v, 564ua 0.4 v cl capacitive load 20 pf tristate digital i/o voh high level output voltage vddd=5v, -633ua 4.5 v vol low level output voltage v ddd=5v, 564ua 0.4 v ioz tristate leakage current to vddd,vssd vddd=5v -1 1 a vih high level input voltage vddd=5v 3.5 v vil low level input voltage vddd=5v 1.5 v ezprg input vprg programming voltage - for factory programming only vddd=5v - - - v 2) supply current isup normal operation vddd=vdda=5v 3 5 ma iaw active wake-up vddd=vdda=5v 40 100 a 3) supply voltage vdda positive analog supply voltage 4.7 5.0 5.3 v 4) vddd positive digital supply voltage 4.5 5.0 5.5 v vss, vssd negative supply voltage 0 v power on reset vporhi power on reset hi 2.5 4.1 v 5) vhyst hysteresis 0.1 0.3 v 5) notes: 1) not tested, derived from device characterization 2) for factory calibration only. during normal operation this pin must be connected to vddd. 3) the average current is dependent on the on-time of the measurement system i.e. it can be programed via the cra register 4) stability of analog supply should be within +/- 0.1 v 5) tested at room temperature only
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 9 of 40 7 functional description 7.1 power on reset the power on reset is iniciated during each power up of the asic and can be triggered purpously by reducing the analog supply v oltage (vdda) to a value lower than vporlo for a time interval longer than 0.5 sec. during power on reset sequence the following steps are performed automatically: - the chip goes to mode mzl (see 7.4) - internal clock is enabled - the calibration constants are loaded from zener-zap memory to the appropriate registers (ztr=>trr, zcl=>car). the load procedur e is directed by the internal clock and can be monitored on intn pin. 188 clock pulses are generated from the internal oscillator so urce. pulse period is equal to internal clock period. after the power-on reset sequence is finished: - the operation continues with internal clock if no external clock is detected. in this case the asics switches to mode mwu with default value of threshold register ( 2 14 ) - if external clock is available the asic switches to mode current measurement mms (default measurement with default configuratio n: gain=100, fovs=4.096mhz, r1=64, mm=4, r2=1, n th =2 14 ). - the microcontroller can communicate via sdi interface whenever ap propriate, i.e. car and trr register can be rewritten from the c if necessary. - because the automatic selected calibration factor (cgi4) is loaded with zeros, the asic delivers constant zero at the output to allow the c to check for an unwanted por. to bring the asic back into normal operation for current measurement with gain100 the c has to copy the cau4 content into the cgi4 factor in the car-register. (see also 7.5.5 and 8.6.2) 7.2 analog part, general description the input signals are level shifted to agnd (+ 2.5 v) then switched by the special high quality mux- which contains also the ch opper ? to the input of the programmable gain amplifier (pga). this low noise amplifier is optimised for best linearity, tc- value and speed at gain 2 4. the systems contains an internal bandgap reference with high stability, low noise and low tc-value. the output of a programmabl e current source can be switched to the analog inputs vbat, ets and etr for testing the sensor connections or for external activation of resistors, bridges or sensors (rtd , ntc). the voltage drop generated by the current is measured a t the corresponding input/output pin. for the wire break test of the rshh and rshl inputs special low noise current sources are implemented. the integrated temperature sensor can also be switched to the pga by the mux and measured any time. the chip temperature can be used for the temperature compensation of the gain of the different channels in the external c, which increases the absolute accuracy considerably. the offset of the amplifier itself is already fairly low, but to guarantee the full dynamic range it can be trimmed via the di gital interface to nearly zero independent of the autozero chopping function. in the same way the manufacturing spread of the absolute value of the reference voltage can be eliminated and the tc-value set to nearly zero by a trimming process via the sdi interface. for more details of the input multiplexer see the following schematic. the position of all switches is defined by writing into the registers cra, crb and crg via the sdi bus, which is explained in 7.5.2 through 7.5.4. internal tempera- ture ad- con- verter pga auxiliary current source m 12 m 13 m 3 m 10 m 14 current source m 2 m 1 m 4 m 15 m 8 m 7 m 9 m 6 etr ets vbat rshh rshl m 5 figure 3: multiplexer
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 10 of 40 7.2.1 reference voltage the asic contains a highly sophisticated precision reference voltage. its typical temperature dependence is a slight parabola s haped curve and is shown in figure 21. this reference voltage is used mainly for the internal ad-converter, but can also be used for external purp oses if the impedance of the external circuitry is high enough. the absolute value and its temperature coefficient (tc) is given by the content of the trr register. this opens the possibility to calibrate the reference voltage to the optimum absolute value (i.e. 1.28 v) and the tc value to zero thus eliminating fully the production spread. writing into subregister trimbv of trr changes the absolute value li nearly by 5.1 mv per digit as shown in the following graph and described in full detail in 7.5.7 trimming the tc value is similarly done by writing into subregister trimbtc. since the tc trimming is also changing the absolu te value it is important to trim the tc first and then the absolute value. 1,16 1,20 1,24 1,28 1,32 1,36 0 5 10 15 20 25 30 content of trimbv in bits reference voltage in v 75 c 24 c 1,12 1,14 1,16 1,18 1,20 1,22 1,24 1,26 10 30 50 70 90 110 resistance load in kohm reference voltage in v measurement open loop value figure 4: reference voltage as function of resistance load fi g ure 5: reference volta g e as function of temperature
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 11 of 40 -250 -200 -150 -100 -50 0 50 100 150 200 0 5 10 15 20 25 30 35 setting of subregister trimbtc of trr temperature coefficient in ppm/k change 12.7 ppm/k per step the tc trimming also opens the unique possibility to change the tc-value within the time of reprogramming of the trr-register ( i.e. within sec) to allow the compensation of different tc-values of the external circuitry for different channels. in addition it can be used for very fast autocalibration of the total tc of a given channel. an external reference voltage is a pplied to the channel to be checked. then all numbers from 0 to 31 are written into subregister trimbtc and a reading is done for the input voltage and the internal temperature as well. the same is repeated at any temperature above rt. from these data the trimbtc setting for a minimum drift can be easil y calculated. 7.2.2 current sources the AS8501 contains several current sources which can be used for checking all input lines for wire brake, to control external circuitry or to activate external sensors. main current source the main current source can be digitally controlled via the content of the crg register in 31 steps of 8 a in the range of 0 t o 248 v. its absolute value can be calibrated by writing in the subregister trimc of trr. the current source can be switched to the inputs vbat, etr or ets to activate external sensors like rtds, ntcs or resistance br iges and strain gages. it can also be used to detect a wire breake of external connected sensors. performing a measurement with a high and a lo w (or zero) current opens the possiblity to eliminate thermal emf voltages in external sensors. secondary current sources the asic contains two other high quality current sources supplying a current of approx. 2a at the inputs rshl and rshh. these current sources can be switched on and off at any time to check the correct connection of both terminals. during off state they must not interfere with the high sensitive voltage inputs, especially the noise level should not be increased. if one of the terminals is an open connection the amplifie r goes into saturation and the overflow bit is set. figure 6: temperature coefficient as function of trimbtc setting
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 12 of 40 7.2.3 internal temperature sensor the asic contains a high sensitive precision temperature sensor which can be used at any time. the sensor supplies a very linea r voltage signal with an offset at 23 degc, which is calibrated and stored in the zzr-register. the voltage can be measured using the internal circui try with gain 6, with free selection of all other parameters defining the sampling rate. the slope of the curve is approx. 75 digits per degc. the calculation of the temperature has to be done in the external c acc. to the following simple formula: tint=( uint(t)-uint(23) ) / 75 + 23c uint(t) is the measured result and uint(23) is the reference value at 23c, which is stored as an 11 bit-word in the zzr-regist er. bits 15, 14 ,13 and 12 will always be the same at room temperature (0101 bin or 20480 dec), therefore it makes no sense to stor e them for each single part. in addition we dont need the high resolution of one digit, which means 1/71.3 = 14 milli kelvin. therefore we cut the las t bit and achieve a word of 11 bit length, which finally is stored in the zzr-register as shown in the ?stored zzr-register mapping? given in 8.6.2 example: value stored in the zzr-register: 1060 dez or 10000100100 bin uint(23) = 0101 10000100100 0 = 22600 dec add register content add if your measured value is : uint(t) = 23767 dec ti[c]= ((23767-22600) / (75 digits / c)) + 23 c = 15.6 c + 23 c = 38.6 c 7.3 digital part in the digital part the result of the ad-converter is processed, i.e. calibration, active offset cancellation and filtering is done. in addition the communication via the serial sdi interface is handled and all circuit functions (like voltage and current path settings, choppi ng, dechopping) are controlled. whenever the power supply line returns from below 2.0 v to above 3.5 v a power-up circuitry is activated which loads the intern al calibration registers from the zener-zap memory into the working register and starts the chip in a special default mode. 7.3.1 sampling rate the sampling rate (sr) is defined by the setting of parameters in register cra or crb. the oversampling frequency (osf), the ov ersampling ratio (osr), the chopping ratio (mm) and the averaging number (av). the sampling rate can be calculated acc. to the following formula: sr= osf/(osr*mm*av) fi g ure 7: measurement of internal temper ature sensor over oil bath temperature 15000 20000 25000 30000 35000 -50 -25 0 25 50 75 100 125 150 175 temperature in deg c internal temperature in digits -100 -75 -50 -25 0 25 50 75 100 inearity deviation in digits output signal linearity deviation cubic fit
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 13 of 40 for an clock frequency of 8.192 mhz it can vary between 16 000 khz and 1.95 hz. in the dual mode the asic is switching automatically between the two channels and it needs at least one measurement for each po larity to get a valid measurement. in addition the asic needs some time to reprogram the internal registers and switches. therefore the maximum sampl ing frequency is limited to 7.5 khz for the above given clock frequency. the internal averaging is not working in the dual mode, but the samplin g frequency can be different for each channel. 7.3.2 calibration the calibration of the asic is done by a test setup as follows: - room temperature calibration of the internal temperature sensor - absolute input-output calibration for all gain settings - tc calibration for the measurement path for gain 24 the absolute input-output calibration of the gain ranges is done that way that for a given input voltage 30 000 digits at the o utput are produced: table 7.2.2 in addition the asic receives an individual 24-bit serial number. the tc-value of the output (total measurement path) for g24 is trimmed to a minimum value by selecting the best setting of the trimbtc subregister of the trr register (see 7.5.7). a similar calibration is done for the other subregisters trimbv, trima and trimc for the absolute value of the reference voltag e, the offset of the pga and the current source respectively. all these data are stored in the zzr register according to the ?stored zzr-register mapping? given in 8.6.2 7.4 modes of operation the AS8501 can run in different operation modes, which are selected and activated via the serial interface. detailed description : mode 0: mzl in power-on reset sequence, which is initiated by the on-chip power-on reset circuit whenever the power is connected , the regi sters are loaded from the zener-zap memory . mode 1 : mms measurement mode where the definition is taken from the registers cra and crg defined later on. the measurements are continuous and measured results are available after the ready flag (intn pin) is set to lo. the result can be read by the c any time after this bit is set to lo. however, to obtain the best noise performances the result should be read when in tn pin is at lo state. all modules are in power-up. mode 2: mmd dual channel measurement mode. two consecutive different measurements are performed according to the settings in the configurat ion registers cra, crb and crg defined later (usually cra defining current measurements and crb voltage measurement). one complete measurement is performed with each setting. crg register holds common settings. the measurements are continuous (a,b,a,b). the 17 th bit in the output register defines, which measurement has been executed according to the definition lo=a, hi=b. the number of consecutive measurements with equal configuration is defined in register crg (bits s3,s2,s1,s0). all modules are in power-up. mode 3: mwu in this wake-up mode the internal clock finclk=256khz is running and one complete measurement is performed in the period from 1 to 1.5 s with the parameter settings of the cra register. before the actual measurement is performed the logic powers up all internal circuits es pecially the agnd and the vref. if the external load is higher than 70 kohms both signals can be used for external triggering or even as interrupt f or the c. if the external clock is not running, this input should be high impedance. to achieve a stable low idle current the oversamplin g ratio should be set to r1=128 and the cfg register must be programmed to x00003, see also 7.5 ?register description?. it is assumed that the thresho ld level in the thr register is defined within the 16 bit range, if not the default value is 210 after one measurement is finished all modules except the on- board oscillator and divider are switched into power down conditio n to save power. the msr register is updated with the last measurement result. whenever this value exceeds the digital threshold the (wake-up) intn pin goes lo for one clock cycle to trigger the wake-up event in the external c. gain input/mv output/digits 1 720 30 000 6 120 30 000 24 30 30 000 50 15 30 000 100 7.5 30 000
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 14 of 40 after that the circuit returns in power-down for approximately 1s. during this time the last measurement (msr register) is avai lable on the sdi interface. in this intermediate sleep-mode all modules except internal osc illator and divider are in power-down mode. the sdi interface wo rks independent which means that the measurement result is available by reading the msr register. at any time the microprocessor can start any other mode via sdi. in such a case the external clock must be switched on first. the chip goes in mwu mode (mode 3) after it received the command for that. after that command 6 or more additional clk pulses a re needed before external clock may go to power down mode (no clk pulses, high level because of internal pull-up resistors). this 6 clk pulses a re needed for synchronisation. on the way back to normal mode this restriction is not needed . mode 4 : mam in this alarm mode the measurement defined in cra is going on. the channel bit in the thr register must be cleared (channel a). the threshold value may be positive or negative. whenever the measured value exceeds the digital threshold value in the thr register the pin intn ( in this mode its function is to signal alarm-condition) goes lo for one clock cycle. for negative threshold value the signed measurement result must be more negative than the thr value to activate the alarm. during measurements the signal intn is high . all modules are in power-up, measurements are continuously going on. mode 5 : mzp zener-zap programming/reading. this mode for factory programming only and should not be used by the customer. mode 6 : mpd power down mode. individual analog blocks can be disabled/enabled. the data acquisition system is not running during this mode is activated. mode 7 : msi the operation in this mode is exactly the same as in mms mode except that the internal clock is used. the sdi interface signals can become active whenever appropriate. this mode can be used if no external clock clk is available. the measuring speed is reduced by a factor of 16. modes 8-15 : these modes are reserved for testing purposes and should not be used by the customer. reading and writing of some registers i s only possible in these higher modes. write to registers car (calibration register) and trr (trimming register) is allowed only in te st modes.
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 15 of 40 modes of operation, register opm mode name description mo3 mo2 mo1 mo0 0 mzl power on, loading from zener-zap memory 0 0 0 0 1 mms single measurement 0 0 0 1 2 mmd double measurement (a,b,a,b ?) 0 0 1 0 3 mwu wake-up 0 0 1 1 4 mam alarm 0 1 0 0 5 mzp zener program/read 0 1 0 1 6 mpd power down 0 1 1 0 7 msi 0 1 1 1 8-15 reserved for testing 1) 1 x x x notes: 1) register addresses 12, 13, 14 and 15 are reserved for testing and future options; operations on these registers must be avoided 7.5 register description in the following sections the register contents and their functions are described in detail. since the length of some registers is too long to present clearly, the registers are logically subdivided according to their functions and described separately. all internal functions are controlled by the contents of these registers which can be reloaded via the serial sdi interface at any time. the AS8501 contains the following registers: register address size contents detailled description see opm 0 4 operating mode register 7.5.1 cra 1 17 measurement a configuration register 7.5.3 crb 2 17 measurement b configuration register 7.5.4 crg 3 28 general configuration register 7.5.2 msr 4 18 measurement result register 7.5.9 zzr 5 188 zener-zap register 7.5.5 car 6 110 calibration register 7.5.6 trr 7 20 trimming register 7.5.7 thr 8 17 alarm or wake-up threshold register 7.5.8 cfg 9 20 test and special configuration register 1) reserved 10-12 test registers note: 1) this register is reserved for testing modes. writing is possible only in mode 8. in order to assure stable conditions in power-down modes mwu(3), mpd(6), tmss(8) and msi(13) the default setting of the cfg register must be changed to x00003. it is not necessary to change this value during normal operation. write commands not supported in a certain mode can be released immediately after the register address. the asic will resume operation with the next start condition. registers car and trr are not buffered. any read operation of the car or trr register may generate transients in the analog circuitry; further accurate measurements require a delay time for settling.
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 16 of 40 7.5.1 opm operation mode register ( 4 bits ) no. bit mo3 mo2 mo1 mo0 note 0 default 0 0 0 0 1) 1) this register has been described in detail under 7.4 7.5.2 crg general configuration register ( 28 bits ) no. crg bits 27-22 21-11 10-7 6-0 note 0 crs cri crv crp subregister crs: sequence length, dechop and chop ( 6 bits ) nr. bits 5 4 3 2 1 0 note 0 crs bit names s3 s2 s1 s0 d c 1) 1 default 0 0 0 1 1 1 2) notes: 1) this register defines the sequence length, chopping (c) and dechopping (d) of the input signal 2) default power-up state before any setting sequence length bits ( 4bits) nr. no. of measurements s3 s2 s1 s0 note 0 16 0 0 0 0 1) 1 1 0 0 0 1 default ? ? ? ? ? ? 14 14 1 1 1 0 15 15 1 1 1 1 notes: 1) number of consecutive measurements of a and b with settings defined in cra,crb and other settings in crg register. this setting is used only for mode mmd. dechopping bit nr. dechopping d note 0 no dechopping 0 1 dechopping 1 chopping bit nr. chopping c note 0 no chopping 0 1 chopping 1 subregister cri: current configuration ( 11 bits ) nr. bits 10 9 8 7 6 5 4 3 2 1 0 note 0 cri bit names m14 m13 m12 m11 m8 m6 i4 i3 i2 i1 i0 1),3) 1 default 0 0 0 0 0 0 0 0 0 0 0 2) 2 output vbat rshl rshh no ets etr notes: 1) whenever m1=1 in (cra,crb) it is good practice to set all m6 to m14 to zero, but it is not mandatory 2) default logic state after power up and before any setting 3) all bits with names m14 to m1 represent control signals of the multiplexer with positive logic (for example m14=1 means that corresponding switch is closed).
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 17 of 40 current source setting bits (5 bits) nr. current [ua] i4 i3 i2 i1 i0 note 0 0 0 0 0 0 0 1 8 0 0 0 0 1 2 16 0 0 0 1 0 3 24 0 0 0 1 1 4 32 0 0 1 0 0 ? ? ? ? ? ? 31 248 1 1 1 1 1 subregister crv: voltage configuration (4 bits ) nr. bits 3 2 1 0 note 0 crv bit names m15 m10 m9 m7 1),3) 1 defaults 0 0 0 0 2) 2 channel vbat- rshl vbat-ets differential ets-rshl etr- rshl notes: 1) this register defines the connection of the analog voltage- bus to the input-pins and to the a/d converter 2) default logic state after power-up and before any setting subregister crp: power down configuration ( 7 bits ) nr. bits p6 p5 p4 p3 p2 p1 p0 note 0 crp bit names pdosc pda pdm pdb pdc pdi pdg 1),3) 1 defaults 0 0 0 0 1 0 0 2) 2 block oscillator amplifier modu- lator ref. bias current source internal temp. analog gnd notes: 1) this register defines the power-down signals of the building blocks 2) default power-up state before any setting 3) the logic is positive (pdosc=1 means the corresponding block is in power-down) 7.5.3 cra measurement channel a configuration register ( 17 bits ) nr. bits 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 note 0 cra bit names cu2 cu1 cu0 m5 m4 m3 m2 m1 g1 g0 f r mm n3 n2 n1 n0 1), 3) 1 defaults 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 2) 2 subreg. cru crm gn osf osr mm crn notes: 1) this register defines the measurement channel a configuration 2) default power-up state before any setting 3) bit m1 is control signal of the multiplexer for current input (for example m1=1 means that corresponding switch is closed).
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 18 of 40 subregister cru: calibration consta nt selection for voltage path ( 3 bits) in registers cra,crb nr. calibration const. u cu2 cu1 cu0 note 0 cau0 0 0 0 1 cau1 0 0 1 2 cau2 0 1 0 3 cau3 0 1 1 4 cau4 1 0 0 5 cau5 1 0 1 6 1548 1 1 0 7 1548 1 1 1 subregister crm: measureme nt path for registers cra,crb nr. bits 13 12 11 10 9 note cra bit names m5 m4 m3 m2 m1 1), 2) 1 defaults 0 0 0 0 1 measurement rshh-rshl 2 0 1 0 0 0 voltage bus 3 0 1 0 1 0 voltage bus, internal temperature 4 0 1 1 0 0 voltage bus, reference low=rshl 5 1 0 0 0 0 voltage bus, gain=1 6 1 0 0 1 0 voltage bus,gain=1, internal temperature 7 1 0 1 0 0 voltage bus, gain=1, reference low=rshl notes: 1) these bits define the inner part of the voltage path settings 2) only the listed combinations are allowed subregister gn: gain defi nition bits, registers cra,crb nr. gain g1 g0 note 0 6 0 0 1 24 0 1 2 50 1 0 3 100 1 1 subregister osf: oversampling frequency bit, registers cra,crb nr. fovs (fclk=8mhz) fovs (internal osc) f note 0 2.048mhz 132khz 0 1) 1 4.096mhz 264khz 1 1) notes: 1) for internal oscillator typical values subregister osr: oversampling ratio bit, registers cra, crb nr. r1 r note 0 64 0 1 128 1
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 19 of 40 subregister mm: chopping ratio bit, registers cra, crb nr. mm mm note 0 4 0 1 8 1 2 1 x 1) notes: 1) for c=0 and d=0 , cho pping and dechopping is switched off and every cycl e is active regardless of mm, i.e. the sampling frequenzy is higher by a factor of 4 subregister crn: averaging bits ( 4 bits), registers cra,crb nr. r2 n3 n2 n1 n0 note 0 1 0 0 0 0 1 2 0 0 0 1 2 4 0 0 1 0 3 8 0 0 1 1 4 16 0 1 0 0 5 32 0 1 0 1 6 64 0 1 1 0 7 128 0 1 1 1 8 256 1 0 0 0 9 512 1 0 0 1 10 1024 1 0 1 0 11-14 reserved for test 1 x x x 1) 15 raw mode 1 1 1 1 2) note: 1) combinations from b to e are reserved for test 2) this mode delivers the ad-values without calibration and averaging but multiplied by a factor which is dependent on the setting of the oversampling ratio. it can be used for high resolution measurements of very low signals since it eliminates the internal rounding error. the ratio between raw result (nr) and normal result (nn) is given by: nr/nn = 2^(11+x)/cal where x=6 for r=128 and x=3 for r=64. cal is the calibration constant used. 7.5.4 crb measurement channel b configuration register ( 17 bits ) nr. bits 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 note 0 crb bit names cu2 cu1 cu0 m5 m4 m3 m2 m1 g1 g0 f r mm n3 n2 n1 n0 1), 3) 1 defaults 0 0 0 0 1 1 0 0 0 1 1 0 0 0 0 0 0 2) 2 subreg. cru crm gn osf osr mm crn notes: 1) this register defines the measurement channel b configuration, the functions of the subregisters are the same as described above for measurement channel a 2) default power-up state before any setting 3) in this mode the chip cannot measure the current sensing input rshh-rshl, therefore m1=0 for all settings
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 20 of 40 7.5.5 zzr zener-zap register (188 bits ) nr. zzr bits 183-187 163-182 53-162 0-52 note 0 zlo ztr zcl ztc 1) 2) notes: 1) 5 bits are reserved for: - 1 bit eventually destroyed during testing, - 2 bits for testing programmed 0 and 1 - 2 bits reserved for locking 2) due to a limited driving capability of the zzr-cells the maximum reading speed is limited to 500 khz subregister zlo: zener spare bits ( 5 bits ) nr. name symbol word width default hex 1 reserved bits zlo 5 f subregister ztr: trimming bits (20 bits) nr. parameter symbol word width default dec 1) unit note 0 tc of reference trimbtc 5 0 bits 1 absolute value of reference trimbv 5 0 bits 2 amplifier offset trima 5 0 bits 3 current source for external temperature trimc 5 0 bits 4 trim bits trimreg 20 bits notes: 1) default values must be written before start of the test subregister zcl: calibration bits ( 110 bits ) nr. parameter symbol word width default dec 3) unit note 0 calibration g=6, i cgi1 11 1548 bits 1),4) 1 calibration g=24, i cgi2 11 1548 bits 1),4) 2 calibration g=50, i cgi3 11 1548 bits 1),4) 3 calibration g=100, i cgi4 11 1548 bits 1),4) 4 calibration u0 cau0 11 1548 bits 1),4) 5 calibration u1 cau1 11 1548 bits 1),4) 6 calibration u2 cau2 11 1548 bits 1),4) 7 calibration u3 cau3 11 1548 bits 1),4) 8 calibration u4 cau4 11 1548 bits 1),4) 9 calibration u5 cau5 11 1548 bits 2),4) 10 cal. bits zcl 110 bits notes: 1) decimal default value of the calibration constant for voltage and current is calculated using formula: cg def =n max /n addef =(v ref *1024)/(v in *g max )=1548 2) default calibration constant for absolute value of the voltage proportional to absolute temperature is the same as for any other range because it uses the same amplifier and max voltage at max. temperature is approx. 150mv and the gain selected must be g0. 3) default values must be written before start of the test 4) calibration constants are selected dependent on state of m1 ( see table below). for m1=1 one of cgi1 to cgi4 is selected according to selected gain of amplifier. for m1=0 the selection of the calibration constants is defined by bits (cu2,cu1,cu0), which are part of cra and crb registers and are defined via sdi interface independently of any other selection.
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 21 of 40 calibration constant selection truth table nr. cu2 cu1 cu0 m1 g1 g0 cal const note 0 x x x 1 0 0 cgi1 1) 1 x x x 1 0 1 cgi2 1) 2 x x x 1 1 0 cgi3 1) 3 x x x 1 1 1 cgi4 1) 4 0 0 0 0 x x cau0 2) 5 0 0 1 0 x x cau1 2) 6 0 1 0 0 x x cau2 2) 7 0 1 1 0 x x cau3 2) 8 1 0 0 0 x x cau4 2) 9 1 0 1 0 x x cau5 2) 10 1 1 0 0 x x 1548 11 1 1 1 0 x x 1548 notes: 1) cgix calibration constants are selected when m1=1 according to selected gain 2) cgux calibration constants are selected when m1=0 according to bits cu2 to cu0 defined via sdi in cra and/or crb registers. subregister ztc: see register mapping 8.2.6
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 22 of 40 7.5.6 car calibration register ( 110 bits ) the calibration register holds the calibration constants that are used by the internal dsp for the correction of each measurement. at power-up sequence the zener-zap subregister zcl is copied into the car register as shown in fig. 7.4.6.1. the register can be read or written in mode 8 via the sdi bus at any time. in particular it is possible to write preliminary calibration constants with car or overwrite the loaded zcl data, if a calibration has been changed. nr. car bits 109-99 98-88 87-77 76-66 65-55 54-44 43-33 32-22 21-11 10-0 note 0 subregister cgi1 cgi2 cgi3 cgi4 cau0 cau1 cau2 cau3 cau4 cau5 1), 2) 1 default 1548 1548 1548 1548 1548 1548 1548 1548 1548 1548 notes: 1) calibration register is composed of the following constants each having 11 bits: cgi1, cgi2, cgi3, cgi4, cau0, cau1, cau2, cau3, cau4, cau5 2) this register can be read or written at any time via the sdi bus. in particular it is possible to write preliminary calibration constants with car or overwrite the loaded zcl data, if a calibration has been changed. 7.5.7 trr trimming register ( 20 bits ) in the trr register the calibration constants for the reference voltage, for the amplifier-offset trim and for the current sour ce setting are stored. at power-up sequence the zener-zap subregister ztr is loaded into the trr register. this register can be read or written in mo de 8 via the sdi bus. in particular it is possible to write preliminary calibration constants into trr or overwrite the loaded ztr data, if a calibration has been changed. the trimming of the trr-registors is usually done at the factory before supplying the part. nr. trr bits 19-15 14-10 9-5 4-0 note 0 subregister trimc trima trimbv trimbtc 1) 1 default 0 0 0 0 notes: 1) writing into trr register is done as usual with the msb first subregister trimc change of current source output with trimc bits nr. trimc0 di/io notes trimcs trimc3 trimc2 trimc1 % 0 0 0 0 0 0 0 1),2) 1 0 0 0 0 1 -1*2.3 1),2) 2 0 0 0 1 0 -2*2.3 1),2) .. .. .. .. .. .. .. 14 0 1 1 1 0 ?14*2.3 1),2) 15 0 1 1 1 1 ?15*2.3 1),2) 16 1 0 0 0 0 16*2.3 1),2) 17 1 0 0 0 1 15*2.3 18 1 0 0 1 0 14*2.3 1),2) .. .. .. .. .. .. .. 30 1 1 1 1 0 2*2.3 1),2) 31 1 1 1 1 1 1*2.3 notes: 1) io is the current in a at trimc = 00000 2) the output current of the internal current source can be controlled in a wide range via the bit setting in crg. in some applica tions it may be necessary to trim the current in the rang of +/- 30% for an optimum result of the external temperature measurement. this trimmi ng is achieved with writing into subregister trimc of the trr register. the trimming is done in % for all ranges selected in crg register.
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 23 of 40 subregister trima change of amplifier offset with trima bits the offset of the pga should be trimmed to a mimimum absolute value to guarantee the full dynamic range with all gain settings. nr. trima0 v offset notes trimas trima3 trima2 trima1 mv 0 0 0 0 0 0 uos 1),2) ,3) 1 0 0 0 0 1 uos -1*1.34 1),2) 2 0 0 0 1 0 uos -2*1.34 1),2) .. .. .. .. .. .. .. 14 0 1 1 1 0 uos ?14*1.34 1),2) 15 0 1 1 1 1 uos ?15*1.34 1),2) 16 1 0 0 0 0 uos 1),2) 17 1 0 0 0 1 uos +1*1.34 18 1 0 0 1 0 uos +2*1.34 1),2) .. .. .. .. .. .. .. 30 1 1 1 1 0 uos +14*1.34 1),2) 31 1 1 1 1 1 uos +15*1.34 notes: 1) uos is the input offset voltage in mv at trima = 00000 2) every step of trima settings brings offset=1.34 mv change in absolute value of the input offset voltage. if the measured value is uos then the number that should be written into the trima for minimum final absolute value is calculated as trima=int((uos)/1.34) for uos above zero and trima=16+int(-uos)/1.34) for uos below zero. 3) the input offset voltage can be measured with chopping and dechopping bits being cleared in register crg. any input channel as well as gain settings can be used. the input should be shorted to avoid any external voltages to interfere with the measurement. if the measured output voltage is va then the offset voltage is calculated acc. vos = va/gain. subregister trimbv change of reference voltage uo with trimbv bits nr. trimbv0 v ref notes trimbvs trimbv3 trimbv2 trimbv1 mv 0 0 0 0 0 0 ua 1),2) 1 0 0 0 0 1 ua -1*5.1 1),2) 2 0 0 0 1 0 ua -2*5.1 1),2) .. .. .. .. .. .. .. 14 0 1 1 1 0 ua ?14*5.1 1),2) 15 0 1 1 1 1 ua ?15*5.1 1),2) 16 1 0 0 0 0 ua 1),2) 17 1 0 0 0 1 ua +1*5.1 18 1 0 0 1 0 ua +2*5.1 1),2) .. .. .. .. .. .. .. 30 1 1 1 1 0 ua +14*5.1 1),2) 31 1 1 1 1 1 ua +15*5.1 notes: 1) ua is the reference voltage in mv at trimbtc = 00000, the optimum value is 1.232v. 2) every step of trimbv settings brings bv =5.1 mv change in absolute value of the reference voltage. for trimming the tc value and absolute value of the reference voltage it is recommended to trim the tc value first and then trim the absolute value since trimbtc is changing both tc and absolute value, whereas trimbv is changing only the absolute value. if the measured absolute value is uam then the number that should be written into the trimbv for optimum final absolute value is calculated as trimbv=int((uam-1.231)/0.0051) for uam above the ideal value and trimbv=16+int(-(uam-1.232)/0.0051) for uam below the ideal value.
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 24 of 40 subregister trimbtc change of reference voltage uo and tc-value with trimbtc bits nr. trimbtc0 v ref tc notes trimbtcs trimbtc3 trimbtc2 1 trimbtc1 1 mv ppm/k 0 0 0 0 0 0 uo tco 1),2) 1 0 0 0 0 1 uo -1*5.2 tco -1*12.7 1),2) 2 0 0 0 1 0 uo -2*5.2 tco -2*12.7 1),2) .. .. .. .. .. .. .. 14 0 1 1 1 0 uo ?14*5.2 tco -14*12.7 1),2) 15 0 1 1 1 1 uo ?15*5.2 tco -15*12.7 1),2) 16 1 0 0 0 0 uo 1),2) 17 1 0 0 0 1 uo +1*5.2 tco +1*12.7 18 1 0 0 1 0 uo +2*5.2 tco -2*12.7 1),2) .. .. .. .. .. .. .. .. 30 1 1 1 1 0 uo +14*5.2 tco -14*12.7 1),2) 31 1 1 1 1 1 uo +15*5.2 tco -15*12.7 notes: 1) uo is the reference voltage in mv and tco is the tc value in ppm/k at trimbv = 00000 2) every step of trimbtc settings brings btc =5.2 mv change in absolute value of the reference voltage and s=12.7 ppm/k change in the slope of temperature dependence. so for trimming the temperature coefficient of the band-gap reference 2 measurements are recommended ( at t 1 =25 o c and at t 2 =125 o c ). if the measured tc value is tcm then the number that should be written into the trimbtc for minimum final tc is calculated as trimbtc=int(tcm/12.7) for positive values and trimbtc=16+int(-tcm/12.7) for negative values. the absolute voltage is also changed in this way, which must be compensated by bringing back the absolute value by changing the trimbv register. usually the trimbvx=-trimbtcx+1 is sufficient. if further accuracy or change of absolute value is necessary it can be adjusted by making some more measurements and adjustments. zzr register: ztr zcl ztc 20 110 53 trr car bit0 bit0 reg.7 reg.6 5 trr car data in b it0 bit0 r/w 18 8 zlo zlo fi g ure 8: cop y in g of zcl and ztr re g isters into car and trr re g isters
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 25 of 40 7.5.8 thr alarm (wake-up) threshold register ( 17 bits ) nr. mr16 mr15 mr14 mr13 mr12 mr11 ? mr1 mr0 note 0 a/b s msb lsb default 0 0 1 0 0 0 1) notes: 1) _ all measurements are performed in channel a therefore mr16 must be set to zero. when channel b is selected no interrupt will be generated. - the signed value is used. for positive thr values the asic will initiate an interrupt whenever the measured value is bigger than the thr value. for negtive thr values the interrupt will be generated for a negative result with an absolute value bigger than the absolute value of the thr register. 7.5.9 msr measurement result register ( 18 bits ) nr. mr17 mr16 mr15 mr14 mr13 mr12 mr11 ? mr1 mr0 note overflow/un derflow a/b s msb lsb 1) notes: 1) - result word length is 16 bits because of calibration accuracy and to maintain all possible resolutions ( different setting ). - a/b bit signifies which measurement was performed: the one defined in cra or crb: mr16=0 -> a mr16=1 -> b - overflow/underflow bit is set whenever the result after multiplication by calibration constant is bigger than 32767 or smaller than ?32767. in wake-up or alarm mode the overflow/under flow always sets intn signal to lo. 8 digital interface description the digital interface of the AS8501 consists of two input pins (clk and sclk) and two i/o pins (intn and sdat). the sclk and sd at pins are used as universal serial data interface (sdi). sdi operates only if external clock signal (clk) is running. 8.1 clk in all operating modes except the wake-up mode this pin must be connected to 8 mhz clock signal. in the wake-up mode (mwu) the clk pin must be connected to logic hi or float. 8.2 intn the intn pin is used to signal various conditions to the microcontroller, depending on the operating mode. application modes of the intn pin mode signal direction purpose note 0 load clock (internal) output indicates progress of the zener-zap load process 1) 1, 2,7 sdi clock disable output signals new result and suggests when to disable sclk in high-precision measurement phase 2) 3 idle / wake-up not output signals the wake-up condition 4 idle / alarm not output signals the alarm condition 5 pw1 input shows the programming pulse width 6,8,9 logic ?0? output no purpose 10 t12 output test mode 10 t18 output test mode notes: 1) 188 clock pulses are generated from the internal oscillator source during the loading time. 2) in measurement modes (mms and mmd) the intn pin is used to synchronize the sdi bus operations (see fig. 9). the trailing edge of intn signals the start of a new measurement.
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 26 of 40 the determination of tcnv and tres from the parameter settings is: tcnv ? r1/(fovs*2) tres = mm*tcnv*r2*2 with r1=osr and r2=number of averages 8.3 sdi bus operation sdi bus is a 2-line bi-directional interface between one master and one slave unit. typically the master unit is a microcontrol ler with software- implemented sdi protocol. the asic is always the slave unit. sdi bus operation is presented on figure 10. during data transfers the sdat signal changes while sclk is low. the sdat signal can change while sclk is high only to generate start or exception conditions. strobe asic the master unit always generates the sclk signal. the master unit generates the sdat signal in start , direction , address , master-write data and exception conditions. the master sdat pin is in high-impedance state in master-read data condition. the slave unit drives the sdat signal only in master-read data condition. in all other cases the slave sdat pin is in high-impedance state. during data transfer in read condition the internal ad-conversion in continuing but the data in the msr-register is not updated and t he output of the intn tres tcnv start measurement i i-1 i+1 i-2 i-1 i available results on sdi sdat sclk start direction data transfer address register data exception figure 9: intn pin in modes 1 and 2 figure 10: sdi bus operation
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 27 of 40 intn signal is suppressed. only after the completion of the reading cycle the asi c returns to the normal condition and updates the msr- register immediately if a new ad-conversion has been finished during data transfer . the master unit does not detect any bus conditions since it generates them. data transfer conditions (direction, register addre ss and register data) must not be changed until the current condition is over. the slave unit does not detect start and exception condition whe n master-read is in progress. the exception condition is reserved for future use and should be avoided. 8.4 data transfers generally the sdi interface is active in all asic modes. for security reasons some write operations are restricted to certain m odes. read operations are never disabled in order to keep consistent sdat driving conditions. writing to the result, trimming and calibration registers (msr, car and trr) is allowed only in test modes. writing to the zener-zap register is allowed only in mode mzp. the first data bit after the start condition in each data transfer defines the data direction: sdat=high is used for master-read data (mr) condition and sdat=low for master-write data (mw) condition. data is transferred with the most significant bit (msb) first. data bits are composed of register address and register data bit s. register address is transmitted first, followed by the register data bits. the register address is always 4 bits long. the number of register da ta bits in table 7.5 is implied by the register address. figure 11: sdi data transfer the asic supports the data transfers presented in table 8.1. master read-write operations register address contents read allowed in modes write allowed in modes page opm 0 operating mode all all cra 1 measurement set-up a all all crb 2 measurement set-up b all all crg 3 general measurement conditions all all msr 4 measurement result all >7 zzr 5 zener-zap data all 5 car 6 calibration register all >7 trr 7 trimming register all >7 thr 8 alarm or wake-up threshold register all all lsb msb a0 a1 a2 a3 register data sclk sdat register address direction mw mr
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 28 of 40 8.5 sdi bus timing timing definitions for sdi bus are based on software-implemented master unit protocol strobe asic strobe c figure 12: sdi bus timing t s ts_m dv_s hi - z hi - z cdd ts_s pw_sc lk ts_ m dv_ m dv_ m lo_sc lk mde master sdat slave sdat (asic) (up) sclk (up)
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 29 of 40 sdi bus timing nr. parameter symbol min typ max unit conditions note 0 sclk pulse width pw_sclk 120 ns all 1 sclk low lo_sclk 120 ns all 5), 6) 2 master sdat exception after sclk mde 120 ns all 3 master sdat valid before/after sclk dv_m 120 tsw ns all 1) 4 slave sdat not valid after sclk dv_s 120 ns master read 5 master 3-state on/off ts_m ts_s tsw ns master read 6 slave 3-state on/off ts_s 120 ns master read 7 bus condition detection disabled in slave unit cdd ns master read 3) notes: 1) tsw is typical time required by the microcontroller program to change or to read the state of the i/o pin 3) start detection is disabled when slave unit transmits data 5) lo_sclk>300ns and pw_sclk> 2sec required to read zzr. 6) lo_sclk > (3/2)*t clk = (3/2)/f clk = (3/2)/8mhz=187.5ns required for results synchronisation in msr. 8.6 sdi access to otp memory sdi can read the otp memory in any mode by reading the register zzr. 8.6.1 zzr register bit mapping cell index 0 1 2 3 4 5 6 7 purpose pos a 1) pos b 2) pos c 3) lock a 4) lock b 5) trimcs trimc3 trimc2 zzr field zlo zlo zlo zlo zlo ztr ztr ztr zzr bit 187 (msb) 186 185 184 183 182 181 180 1) always programmed to '0' during the production test 2) always programmed to '0' during the production test 3) always programmed to '1' during the production test 4) reserved 5) reserved
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 30 of 40 cell index 8 9 10 11 12 13 14 15 purpose trimc1 trimc0 trimas trima3 trima2 trima1 trima0 trimbvs zzr field ztr ztr ztr ztr ztr ztr ztr ztr zzr bit 179 178 177 176 175 174 173 172 cell index 16 17 18 19 20 21 22 23 purpose trimbv3 trimbv2 trimbv1 trimbv0 trimbtcs trimbtc3 trimbtc2 trimbtc1 zzr field ztr ztr ztr ztr ztr ztr ztr ztr zzr bit 171 170 169 168 167 166 165 164 cell index 24 25 26 27 28 29 30 31 purpose trimbtc0 cgi1_10 cgi1_9 cgi1_8 cgi1_7 cgi1_6 cgi1_5 cgi1_4 zzr field ztr zcl zcl zcl zcl zcl zcl zcl zzr bit 163 162 161 160 159 158 157 156 cell index 32 33 34 35 36 37 38 39 purpose cgi1_3 cgi1_2 cgi1_1 cgi1_0 cgi2_10 cgi2_9 cgi2_8 cgi2_7 zzr field zcl zcl zcl zcl zcl zcl zcl zcl zzr bit 155 154 153 152 151 150 149 148 cell index 40 41 42 43 44 45 46 47 purpose cgi2_6 cgi2_5 cgi2_4 cgi2_3 cgi2_2 cgi2_1 cgi2_0 cgi3_10 zzr field zcl zcl zcl zcl zcl zcl zcl zcl zzr bit 147 146 145 144 143 142 141 140 cell index 48 49 50 51 52 53 54 55 purpose cgi3_9 cgi3_8 cgi3_7 cgi3_6 cgi3_5 cgi3_4 cgi3_3 cgi3_2 zzr field zcl zcl zcl zcl zcl zcl zcl zcl zzr bit 139 138 137 136 135 134 133 132 cell index 56 57 58 59 60 61 62 63 purpose cgi3_1 cgi3_0 cgi4_10 cgi4_9 cgi4_8 cgi4_7 cgi4_6 cgi4_5 zzr field zcl zcl zcl zcl zcl zcl zcl zcl zzr bit 131 130 129 128 127 126 125 124 cell index 64 65 66 67 68 69 70 71 purpose cgi4_4 cgi4_3 cgi4_2 cgi4_1 cgi4_0 cau0_10 cau0_9 cau0_8 zzr field zcl zcl zcl zcl zcl zcl zcl zcl zzr bit 123 122 121 120 119 118 117 116
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 31 of 40 cell index 72 73 74 75 76 77 78 79 purpose cau0_7 cau0_6 cau0_5 cau0_4 cau0_3 cau0_2 cau0_1 cau0_0 zzr field zcl zcl zcl zcl zcl zcl zcl zcl zzr bit 115 114 113 112 111 110 109 108 cell index 80 81 82 83 84 85 86 87 purpose cau1_10 cau1_9 cau1_8 cau1_7 cau1_6 cau1_5 cau1_4 cau1_3 zzr field zcl zcl zcl zcl zcl zcl zcl zcl zzr bit 107 106 105 104 103 102 101 100 cell index 88 89 90 91 92 93 94 95 purpose cau1_2 cau1_1 cau1_0 cau2_10 cau2_9 cau2_8 cau2_7 cau2_6 zzr field zcl zcl zcl zcl zcl zcl zcl zcl zzr bit 99 98 97 96 95 94 93 92 cell index 96 97 98 99 100 101 102 103 purpose cau2_5 cau2_4 cau2_3 cau2_2 cau2_1 cau2_0 cau3_10 cau3_9 zzr field zcl zcl zcl zcl zcl zcl zcl zcl zzr bit 91 90 89 88 87 86 85 84 cell index 104 105 106 107 108 109 110 111 purpose cau3_8 cau3_7 cau3_6 cau3_5 cau3_4 cau3_3 cau3_2 cau3_1 zzr field zcl zcl zcl zcl zcl zcl zcl zcl zzr bit 83 82 81 80 79 78 77 76 cell index 112 113 114 115 116 117 118 119 purpose cau3_0 cau4_10 cau4_9 cau4_8 cau4_7 cau4_6 cau4_5 cau4_4 zzr field zcl zcl zcl zcl zcl zcl zcl zcl zzr bit 75 74 73 72 71 70 69 68 cell index 120 121 122 123 124 125 126 127 purpose cau4_3 cau4_2 cau4_1 cau4_0 cau5_10 cau5_9 cau5_8 cau5_7 zzr field zcl zcl zcl zcl zcl zcl zcl zcl zzr bit 67 66 65 64 63 62 61 60 cell index 128 129 130 131 132 133 134 135 purpose cau5_6 cau5_5 cau5_4 cau5_3 cau5_2 cau5_1 cau5_0 tcu1_8 zzr field zcl zcl zcl zcl zcl zcl zcl ztc zzr bit 59 58 57 56 55 54 53 52
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 32 of 40 cell index 136 137 138 139 140 141 142 143 purpose tcu1_7 tcu1_6 tcu1_5 tcu1_4 tcu1_3 tcu1_2 tcu1_1 tcu1_0 zzr field ztc ztc ztc ztc ztc ztc ztc ztc zzr bit 51 50 49 48 47 46 45 44 cell index 144 145 146 147 148 149 150 151 purpose tcu0_8 tcu0_7 tcu0_6 tcu0_5 tcu0_4 tcu0_3 tcu0_2 tcu0_1 zzr field ztc ztc ztc ztc ztc ztc ztc ztc zzr bit 43 42 41 40 39 38 37 36 cell index 152 153 154 155 156 157 158 159 purpose tcu0_0 trt0_10 trt0_9 trt0_8 trt0_7 trt0_6 trt0_5 trt0_4 zzr field ztc ztc ztc ztc ztc ztc ztc ztc zzr bit 35 34 33 32 31 30 29 28 cell index 160 161 162 163 164 165 166 167 purpose trt0_3 trt0_2 trt0_1 trt0_0 tcn3_7 tcn3_6 tcn3_5 tcn3_4 zzr field ztc ztc ztc ztc ztc ztc ztc ztc zzr bit 27 26 25 24 23 22 21 20 cell index 168 169 170 171 172 173 174 175 purpose tcn3_3 tcn3_2 tcn3_1 tcn3_0 tcn2_7 tcn2_6 tcn2_5 tcn2_4 zzr field ztc ztc ztc ztc ztc ztc ztc ztc zzr bit 19 18 17 16 15 14 13 12 cell index 176 177 178 179 180 181 182 183 purpose tcn2_3 tcn2_2 tcn2_1 tcn2_0 tcn1_7 tcn1_6 tcn1_5 tcn1_4 zzr field ztc ztc ztc ztc ztc ztc ztc ztc zzr bit 11 10 9 8 7 6 5 4 cell index 184 185 186 187 purpose tcn1_3 tcn1_2 tcn1_1 tcn1_0 zzr field ztc ztc ztc ztc zzr bit 3 2 1 0
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 33 of 40 8.6.2 stored zzr-register mapping zzr-register zzr subregister 109876543210 msb lsb zlo x x x x x 187 183 trimc x x x x x 182 178 current source calibration trima x x x x x 177 173 pga offset calibration trimbv x x x x x 172 168 reference voltage calibration trimbtc x x x x x 167 163 tc calibration cgi1 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 162 152 gain 6 currrent 1500a cgi2 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 151 141 gain 24 current 300 a cgi3 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 140 130 gain 50 current 150 a cgi4 00000000000 129119 gain100 current 75 a cau0 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 118 108 calibration factor for gain 24 cau1 11111111111 10797 cau2 11111111111 9686 cau3 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 85 75 calibration factor for gain 1 cau4 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 74 64 calibration factor for gain 100 cau5 ct ct ct ct ct ct ct ct ct ct ct 63 53 calibration factor for internal temperature tcu1 1 cscscscscscscscs 52 44 8 bits for checksum 1) tcu0 1 1 1 fi fi fi fi fi fi 43 35 6 bits for internal clock 2) trt0 ttttttttttt 342411 bits for internal temperature at 23c tcn3 n23nnnnnnn 2316 high byte for serial number tcn2 nnnnnnnn 15 8 medium byte for serial number tcn1 nnnnnnnn0 7 0 low byte for serial number x = these fields are written during calibration c0 = these fields are written during calibration of g6 c1 = these fields are written during calibration of g24 (i.e. 30 mv = 30 000 digits) 0 = zero value of calibration constant for detection of unwanted por ct = calibration factor for slope of tint : 75 digits/deg cs = 8-bit checksum for zzr-register fi = 6-bit for calibration of internal clock t = 11 bits for tint value at 23 c nr = 24 bits serial number ztc bit no. in subregister zzr-bits remarks zcl ztr notes: 1) the checksum contains the added value of all bits in the zzr register without the 6 checksum bits 2) tthe internal clock frequency can be calculated int_fclk= (240 + 6-bit fi-number) khz
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 34 of 40 9 general application hints since the AS8501 is optimised for low voltage applications extreme care should be taken that the signal is not disturbed by inf luences like bad ground reference, external noise pick-up, thermal emfs generated at the transition of different materials or ground loops. the influen ce of these error sources can be quite high and they may completely shadow the excellent properties of the device if not handled properly. the following sections are supposed to supply additional informations to the design engineer how to get around some of these problems. 9.1 ground connection, analog common the analog common termi nal where all voltages are referring to is rshl. all ground lines of the external circuitry of vbat, ets and etr as well as the voltage sense line of the low ohmic current sensing resistor should be connected to each other in a star like ground point. it is recommended that this point is as close as possible situated to the low side sense terminal of the current sensing resistor. it should also be connec ted to the vss and vssd terminal, but the return line of both must leave this point separately. also the power decoupling capacitors should be connect ed to the analog common. to give an example of the magnitude of possible errors consider that the ground return of the power supply is not connected pro perly and 5 mm of a copper track 35m thick and 0.1 mm wide are within the measuring circuit with a current flow of 5 ma. this will result in an of fset of 120 v which is more than 500 times higher than the typical offset of the asic. in addition the current fluctuations will act as an extra noise voltage which is also way above that of the device itself. 9.2 thermal emf another major source of error for low level measurements are thermal voltages (electromotive force, thermal emf) or seebeck vo ltages which are principally produced by any junction of two dissimilar materials. on pc-boards pairs of dissimilar materials may consist of the copper tracks and the solder, the leads of different components or different materials used in the construction within the components. any temperatu re difference between two connection produces a voltage which is superimposed to the measuring voltage. a number of strategies are known to detect or minimise their influence on the measuring result: - in cases were a current has to be measured directly or a current is to be used to activate a resistive sensor (like ohm-meter or temperature measurement with rtds, ntc or ptc) a switch in the circuit could be used to interrupt or invert the c urrent thus producing a current change di. in the difference of the two voltage states du the emfs as well as the offset voltages of the am plifier are fully eliminated. for resistance measurements this method is known as ?true ohm? measurement. - in applications were this is not possible and the problematic device (i.e. the input resistor of an amplifier) can be located i t may help to place a dummy device of the same type in the circuit as close and thermally connected as good as possible to compensate the influence o f the first one. - since the thermal emfs are proportional to the temperature difference it is important to maintain a homogeneous temperature dis tribution in the vicinity of the sensitive area. this is possible by keeping this area as small as possible, by avoiding any heat sources nearby or by increasing the heat conductivity of the substrate, i.e. wide and th ick copper tracks, multilayer bo ard or even metal substrate. - the best solution of all however is to avoid the thermal emfs by using only components which are matched to the copper world wh ich means that their thermo-electrical power against copper is zero. this is specially important for current measurements in the range of 10- 1000a. in this case the resistance value has to be very low (down to 100ohms) to limit the measuring power and avoid an overheating of the se nsing resistor. on the other hand the voltages to be detected are extremely low if a high resolution is required. if for instance a current of 10 ma has to be measured with a 100ohm resistor, the resolu tion of the measuring system must be bette r than 1v and the error voltages due to thermal emfs must be below this limit. quite often people are trying to use the well known konstantan (cuni44) for current sensing resistors . this is a bad choice since the thermal emf versus copper is very high. with ?40v/deg already a temperature difference of 2.5 k is enough to produce an error which is 100 times lager than the required resolution. or vice versa a temperature fluctuat ion of only 1/100 k produces a ?thermal noise? which is equivalent to the required resolution. with such materials and high currents of 10a and above the other thermoelectric effect, the so called peltier-effect, can also play an important role. under current flow this effect generates heat in one junction and destroys the same amount of heat in the other junction . the amount of heat is proportional to the current and its direction. the result is a temperature difference which in turn generates a thermal emf proportional to it. finally this means that such a resistor produces its own error voltage and it is never possible to measure better than 1-2% wit h such badly matched materials. the precision resistance materials manganin, zeranin and isaohm are perfectly matched to the copper world an d resistors made from these materials can achieve the high quality that is necessary for low
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 35 of 40 level measurements and high resolution . 9.3 noise considerations for every low level measuring system it is essential to know the origin of noise and to accept the limitations given by it. thr ee major sources of noise have to be considered. the input voltage noise and the input current noise of the amplifier and the thermal noise (johnson nois e) of resistors in the external circuitry around the amplifier. due to the fact that these three sources are not correlated they can be added in the w ell known square root equation. in most applications the input resistor or input divider is low ohmic (i.e. below 10 kohms) which mean that the noise voltage produced by the input current noise is negligible compared to the input voltage noise. the input noise density (en) of the AS8501 is with only 35 nv /sqr(hz) extremely low. this could be achieved with a special internal analog and digital chopper circuitry which eliminates the cmos typical 1/f-noise completely. even though the overall noise will be dominated by the input amplifier as long as the external resistors are below 10 kohm. the total noise voltage generated at a given frequency resp. in a given frequency band (bw) is given by: un= en*sqr(bw) this square root dependence can be seen very nicely in fig. 9.10. the typical square-root shaped dependence is found for both t he peak to peak noise as well as for the equivalent rms noise. the bandwidth resp. the sampling frequency of the AS8501 can be adapted to the requirements of the application by programming t he internal digital filter via the sdi bus. for a sampling frequency of 16khz the input voltage rms noise is less than 5v, whereas at 500 hz alrea dy 1v (or 1lsb) is reached. if the customer needs even higher resolution at a lower measuring speed the internal integration time can be further increased but due to the limitation of the digital noise ( 1lsb) it is better to perform an external averaging in the attached c. in this way the resolution of th e system can be considerably increased to less than 0.1 v for sampling rates of 5 hz and below which corresponds to an effective ad-converter width of mor e than 20 bits. (see fig. 9.10) 9.4 shielding, guarding in many applications it is difficult to gain full benefit from the AS8501 performance since a number of external error sources can disturb the measurement. to achieve the maximum performance the design engineer has to take care specially of the layout of the pc-board an d the sense connections to the external compon ents. to avoid noise pick-up from external magn etic fields all tracks on the pc-board should be parallel strip lines and they should be traced as close as possible to each other. external sensing cables should be twisted and kept away from curr ent carrying cables as far as possible. for longer cables a shielding is sometimes helpful but care should be taken that the shield is not connected t o one of the sense leads. for an optimum performance it should be open on one side, the other side should be connected to the central (star like) analog common point. in very sensitive applications it may be wise to use a guard ring around both inputs and it should be connected again to the an alog common point. this procedure minimises leakage currents and parasitic capacitances between different terminals and components on the pc-board. emv interferences can be affectively avoided in most cases by using standard smd-type high frequency filters in the analog inpu t lines as well as in the digital output lines.
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 36 of 40 parameters: 300a, g24, av4, osf 2.048, osr 128 -0,5 -0,3 0,0 0,3 0,5 -25,0 0,0 25,0 50,0 75,0 100,0 125,0 temperature in deg c linearity deviation in % 250 a 15 ma 0 a -150 a -250 a figure 14: linearity deviation for different currents over temperature 10 typical performance characteristics parameters: 300a, g24, av4, osf 2.048, osr 128 29990 29995 30000 30005 30010 0 500 1000 1500 2000 measurement no. output in digits figure 16: resolution and noise at 95% full scale, sampling rate: 1khz parameters: 300a, g24, av32, osf 2.048, osr 128 -10 -5 0 5 10 0 500 1000 1500 2000 measurement no. output in digits figure 13: resolution and noise at zero input, sampling rate: 1khz dual channel measurement, sampling rate f=8 khz -10000 -5000 0 5000 10000 200 220 240 260 280 measurement number output / digits rshh-rshl 100hz square vbat 220hz sine figure 17: dual mode measurement parameters: 300a, g24, av4, osf 2.048, osr 128 -0,03 -0,02 -0,01 0,00 0,01 0,02 0,03 -400 -300 -200 -100 0 100 200 300 400 input current in a linearity deviation in % figure 15: linearity deviation over input signal g24,av=4,1000hz, external averaging 0,01 0,1 1 10 1 10 100 1000 10000 final frequency in hz noise in digits or v 2.048 mhz 4.096 mhz 'best chopper opa of the world' peak to peak sigma pp figure 18: output voltage noise over sampling rate
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 37 of 40 ihm-a-1500 parameters: gain24, sampling rate 125 hz -20 -15 -10 -5 0 5 10 15 20 02,5 57,510 time in sec output in digits figure 21: noise at 125 hz sampling rate, gain 24 -5,0 -2,5 0,0 2,5 5,0 -50 -25 0 25 50 75 100 125 temperature deg c change in % g6 g24 g50 g100 figure 20: typical output as function of temperature for all gains -2,0 -1,5 -1,0 -0,5 0,0 0,5 1,0 1,5 2,0 -50 -25 0 25 50 75 100 125 temperature deg c change in % g6 g24 figure 19: typical output as function of temperature for gains 6 and 24 ihm-a-1500 temperature dependence of reference voltage -0,4 -0,2 0,0 0,2 0,4 -40 -20 0 20 40 60 80 100 120 temperature in c change in % original figure 23: temperature dependence of internal reference voltage (not trimmed) ihm-a-1500 300a, g24, av1, osf 2.048, osr 128 -2500 -2000 -1500 -1000 -500 0 500 1000 1500 2000 2500 0 1020304050 measurement no. output in digits ac input f requency 100 hz figure 22: real time ac measurement at 100 hz
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 38 of 40 11 package dimensions thermal resistance junction / ambient.: 66 k/w (typ.) in still air 12 revision history revision date description 1.0 1.1 feb.10,2006 march 23, 2006 initial revision r thja 13 ordering information delivery in tape and reel (1 reel = 1500 devices) order AS8501 t&r delivery in tubes (1 tube = 46 devices) order AS8501 tub
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 39 of 40 14 contact 14.1 headquarters austriamicrosystems ag a 8141 schloss premst?tten, austria phone: +43 3136 500 0 fax: +43 3136 525 01 industry.medical@austriamicrosystems.com www.austriamicrosystems.com 14.2 sales offices austriamicrosystems germany gmbh tegernseer landstrasse 85 d-81539 mnchen, germany phone: +49 89 69 36 43 0 fax: +49 89 69 36 43 66 austriamicrosystems italy s.r.l. via a. volta, 18 i-20094 corsico (mi), italy phone: +39 02 4586 4364 fax: +39 02 4585 773 austriamicrosystems france s.a.r.l. 124, avenue de paris f-94300 vincennes, france phone: +33 1 43 74 00 90 fax: +33 1 43 74 20 98 austriamicrosystems switzerland ag rietstrasse 4 ch 8640 rapperswil, switzerland phone: +41 55 220 9008 fax: +41 55 220 9001 austriamicrosystems uk, ltd. 88, barkham ride, finchampstead, wokingham berkshire rg40 4et, united kingdom phone: +44 118 973 1797 fax: +44 118 973 5117 austriamicrosystems ag klaavuntie 9 g 55 fi 00910 helsinki, finland phone: +358 9 72688 170 fax: +358 9 72688 171 austriamicrosystems ag biv?gen 3b s 19163 sollentuna, sweden phone: +46 8 6231 710 austriamicrosystems usa, inc. 8601 six forks road suite 400 raleigh, nc 27615, usa phone: +1 919 676 5292 fax: +1 509 696 2713 austriamicrosystems usa, inc. 4030 moorpark ave suite 116 san jose, ca 95117, usa phone: +1 408 345 1790 fax: +1 509 696 2713 austriamicrosystems ag suite 811, tsimshatsui centre east wing, 66 mody road tsim sha tsui east, kowloon, hong kong phone: +852 2268 6899 fax: +852 2268 6799 austriamicrosystems ag aios gotanda annex 5 th fl., 1-7-11, higashi-gotanda, shinagawa-ku tokyo 141-0022, japan phone: +81 3 5792 4975 fax: +81 3 5792 4976 austriamicrosystems ag #805, dong kyung bldg., 824-19, yeok sam dong, kang nam gu, seoul korea 135-080 phone: +82 2 557 8776 fax: +82 2 569 9823 austriamicrosystems ag singapore representative office 83 clemenceau avenue, #02-01 ue square 239920, singapore phone: +65 68 30 83 05 fax: +65 62 34 31 20
AS8501 - preliminary data sheet austria micro systems revision 1.1, 04-april-06 www.austriamicrosystems.com page 40 of 40 disclaimer devices sold by austriamicrosyst ems ag are covered by the warr anty and patent ident ification provisions appearing in its term o f sale. austriamicrosystems ag makes no warranty, express, statutory, implied, or by description r egarding the information set forth herein or regarding the freedom of the described devi ces from patent infringement. austr iamicrosystems ag reserves the right to change specifications and prices at any time and without notice. therefore, prior to designing this product into a sys tem, it is necessary to check with austriamicrosystems ag for current information. this product is intended for use in normal comme rcial applications. applications requiring extended temperature ra nge, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment ar e specifically not recommended without addi tional processing by austriamicro systems ag for each application. the information furnished here by austriami crosystems ag is believed to be correct and accurate. however, austriamicrosystems a g shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the fu rnishing, performance or use of the techni cal data herein. no obligation or liabilit y to recipient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or other services. copyright devices sold by austriamicrosystems are co vered by the warranty and patent indemnification provisions appearing in its term of sale. austriamicrosystems makes no warranty, express, statutory, implied, or by description r egarding the information set forth herein or regarding the freedom of the described devi ces from patent infringement. austria microsystems reserves the right to change specifications and prices at any time and without not ice. therefore, prior to desi gning this product into a system, i t is necessary to check with austriamicrosystems for current information. this product is intended fo r use in normal commercial applications. copyright ? 2004 austriamicrosystems. trademar ks registered ?. all rights reserved. t he material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. to the best of its knowledge, austriamicr osystems asserts that t he information containe d in this publication is accurate and correct. however, austriamicrosystems shall not be liable to recipient or any third party for any dam ages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in c onnection with or arising out of the furni shing, performance or use of the technical data herein. no obligation or liability to recipient or any third party shall arise or flow out of austriamicro systems rendering of tec hnical or other ser vices.

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